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| The SAM47 instruction set is specifically designed to support the large register files typically founded in most KS57-series microcontrollers. The SAM47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the instruction operand in place of the actual address. Other important features of the SAM47 instruction set include: -- 1-byte referencing of long instructions (REF instruction) -- Redundant instruction reduction (string effect) -- Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction. Several instructions have multiple operand formats. Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb, b, and so on. Using instruction labels can greatly simplify programming and debugging tasks. In this section, the following SAM47 instruction set features are described in detail: -- Instruction reference area -- Instruction redundancy reduction -- Flexible bit manipulation -- ADC and SBC instruction skip condition !"#$"#$%&&$ %&&' ( ) * + INSTRUCTION REFERENCE AREA Using the 1-byte REF (Reference) instruction, you can reference instructions stored in addresses 0020H-007FH of program memory (the REF instruction look-up table). The location referenced by REF may contain either two 1byte instructions or a single 2-byte instruction. The starting address of the instruction being referenced must always be an even number. 3-byte instructions such as JP or CALL may also be referenced using REF. To reference these 3-byte instructions, the 2-byte pseudo commands TJP and TCALL must be written in the reference instead of JP and CALL. The PC is not incremented when a REF instruction is executed. After it executes, the program's instruction execution sequence resumes at the address immediately following the REF instruction. By using REF instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce program size. To summarize, the REF instruction can be used in three ways: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions; -- Branching to any location by referencing a branch address that is stored in the look-up table; -- Calling subroutines at any location by referencing a call address that is stored in the look-up table. If necessary, a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence. In addition, the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions. Two-byte instruction can be referenced by using a REF instruction (An exception is XCH A, DA). If the MSB value of the first one-byte instruction in the reference area is "0", the instruction cannot be referenced by a REF instruction. Therefore, if you use REF to reference two 1-byte instruction stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. These combination examples are described in Table 5-1. Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups First 1-Byte Instruction Instruction LD Operand A, #im Second 1-Byte Instruction Instruction INCS INCS DECS LD A, @RRa INCS INCS DECS LD @HL, A INCS INCS DECS ,* -./ Operand R RRb R R RRb R R RRb R REDUCING INSTRUCTION REDUNDANCY When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled like a NOP instruction. When LD HL,#imm instructions are used consecutively, redundant instructions are also ignored. In the following example, only the 'LD A, #im' instruction will be executed. The 8-bit load instruction which follows it is interpreted as redundant and is ignored: LD LD A,#im EA,#imm ; Load 4-bit immediate data (#im) to accumulator ; Load 8-bit immediate data (#imm) to extended ; accumulator In this example, the statements 'LD A,#2H' and 'LD A,#3H' are ignored: BITR LD LD LD LD EMB A,#1H A,#2H A,#3H 23H,A ; ; ; ; Execute instruction Ignore, redundant instruction Ignore, redundant instruction Execute instruction, 023H #1H If consecutive LD HL, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, HL) are detected, only the first LD is executed and the LDs which immediately follow are ignored. For example, LD LD LD LD LD HL,#10H HL,#20H A,#3H EA,#35H @HL,A ; ; ; ; ; HL 10H Ignore, redundant instruction A 3H Ignore, redundant instruction (10H) 3H If an instruction reference with a REF instruction has a redundancy effect, the following conditions apply: -- If the instruction preceding the REF has a redundancy effect, this effect is cancelled and the referenced instruction is not skipped. -- If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped. PROGRAMMING TIP -- ABC ORG LD ORG Example of the Instruction Redundancy Effect ; Stored in REF instruction reference area 0020H EA,#30H 0080H LD REF EA,#40H ABC ; Redundancy effect is encountered ; No skip (EA #30H) REF LD ABC EA,#50H ; EA #30H ; Skip FLEXIBLE BIT MANIPULATION In addition to normal bit manipulation instructions like set and clear, the SAM47 instruction set can also perform bit tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit addressing modes. Three types of bit addressing are supported: -- mema.b -- memb.@L -- @H+DA.b The parameters of these bit addressing modes are described in more detail in Table 5-2. Table 5-2. Bit Addressing Modes and Parameters Addressing Mode mema.b memb.@L @H+DA.b Ports BSCx, Ports All bit-manipulatable peripheral hardware Addressable Peripherals ERB, EMB, IS1, IS0, IEx, IRQx FB0H-FBFH FF0H-FFFH FC0H-FFFH All bits of the memory bank specified by EMB and SMB that are bit-manipulatable Address Range , 0 *% The following instructions have a skip function when an overflow or borrow occurs: XCHI XCHD LDI LDD INCS DECS ADS SBS If there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. However, the carry flag value is unaffected. The instructions BTST, BTSF, and CPSE also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. INSTRUCTIONS WHICH AFFECT THE CARRY FLAG The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: ADC SBC SCF RCF CCF RRC ADC AND SBC INSTRUCTION SKIP CONDITIONS The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ADS A,#im'. If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function. If, however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction, the ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS, and program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL' and 'SBC A,@HL' skip feature. LDB BAND BOR BXOR IRET C,(operand) C,(operand) C,(operand) C,(operand) Table 5-3. Skip Conditions for ADC and SBC Instructions Sample Instruction Sequences ADC A,@HL ADS A,#im xxx xxx SBC A,@HL ADS A,#im xxx xxx 1 2 3 4 1 2 3 4 If the result of instruction 1 is: Overflow No overflow Borrow No borrow Then, the execution sequence is: 1, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 3, 4 Reason ADS cannot skip instruction 3, even if it has a skip function. ADS cannot skip instruction 3, even if it has a skip function. Table 5-4. Data Type Symbols Symbol d a b r f i t Data Type Immediate data Address data Bit data Register data Flag data Indirect addressing data memc x 0.5 immediate data DA @ src dst (R) .b im imm # Table 5-5. Register Identifiers Full Register Name 4-bit accumulator 4-bit working registers 8-bit extended accumulator 8-bit memory pointer 8-bit working registers Select register bank 'n' Select memory bank 'n' Carry flag Program status word Port 'n' 'm'-th bit of port 'n' Interrupt priority register Enable memory bank flag Enable register bank flag A E, L, H, X, W, Z, Y EA HL WX, YZ, WL SRB n SMB n C PSW Pn Pn.m IPR EMB ERB SB XOR OR AND [(RR)] ID ADR ADRn R Ra RR RRa RRb RRc mema memb memc Table 5-6. Instruction Operand Notation Symbol Definition Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4-bit immediate data (number) 8-bit immediate data (number) Immediate data prefix 000H-3FFFH immediate address 'n' bit address A, E, L, H, X, W, Z, Y E, L, H, X, W, Z, Y EA, HL, WX, YZ HL, WX, WL HL, WX, YZ WX, WL FB0H-FBFH, FF0H-FFFH FC0H-FFFH Code direct addressing: 0020H-007FH Select bank register (8 bits) Logical exclusive-OR Logical OR Logical AND Contents addressed by RR Table 5-7. Opcode Definitions (Direct) Register A E L H X W Z Y EA HL WX YZ r2 0 0 0 0 1 1 1 1 0 0 1 1 r1 0 0 1 1 0 0 1 1 0 1 0 1 r0 0 1 0 1 0 1 0 1 0 0 0 0 Table 5-8. Opcode Definitions (Indirect) Register @HL @WX @WL i2 1 1 1 i1 0 1 1 i0 1 0 1 12 12 A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected using the PCON register. In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped -- whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB instructions. The values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows: Case 1: No skip Case 2: Skip is 1-byte or 2-byte instruction Case 3: Skip is 3-byte instruction S = 0 cycles S = 1 cycle S = 2 cycles , 34 ) This section contains a high-level summary of the SAM47 instruction set in table format. The tables are designed to familiarize you with the range of instructions that are available in each instruction category. These tables are a useful quick-reference resource when writing application programs. If you are reading this user's manual for the first time, however, you may want to scan this detailed information briefly, and then return to it later on. The following information is provided for each instruction: -- Instruction name -- Operand(s) -- Brief operation description -- Number of bytes of the instruction and operand(s) -- Number of machine cycles required to execute the instruction The tables in this section are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions Table 5-9. CPU Control Instructions -- High-Level Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand - Operation Description Set carry flag to logic one Reset carry flag to logic zero Complement carry flag Enable all interrupts Disable all interrupts Engage CPU idle mode Engage CPU stop mode No operation Select memory bank Select register bank Reference code Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location Bytes 1 1 1 2 2 2 2 1 2 2 1 2 Cycles 1 1 1 2 2 2 2 1 2 2 3 2 Table 5-10. Program Control Instructions -- High-Level Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR LJP JP JPS JR ADR ADR ADR #im @WX @EA LCALL CALL CALLS RET IRET SRET ADR ADR ADR - - - Operation Description Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Long jump to direct address (15 bits) Jump to direct address (14 bits) Jump direct in page (12 bits) Jump to immediate address Branch relative to WX register Branch relative to EA Long call direct in page (15 bits) Call direct in page (14 bits) Call direct in page (11 bits) Return from subroutine Return from interrupt Return from subroutine and skip Bytes 2 2 2 1 2 2 3 3 2 1 2 2 3 3 2 1 1 1 Cycles 2+S 2+S 2+S 1+S 2+S 2+S 3 3 2 2 3 3 4 4 3 3 3 3+S Table 5-11. Data Transfer Instructions -- High-Level Summary Name XCH Operand A,DA A,Ra A,@Rra EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@Rra A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH POP A,@HL A,@HL EA,@WX EA,@EA A RR SB RR SB Operation Description Exchange A and direct data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Exchange A and indirect data memory contents; increment contents of register L and skip on carry Exchange A and indirect data memory contents; decrement contents of register L and skip on carry Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Load indirect data memory to A; increment register L contents and skip on carry Load indirect data memory contents to A; decrement register L contents and skip on carry Load code byte from WX to EA Load code byte from EA to EA Rotate right through carry bit Push register pair onto stack Push SMB and SRB values onto stack Pop to register pair from stack Pop SMB and SRB values from stack Bytes 2 1 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 1 1 1 1 1 1 2 1 2 Cycles 2 1 1 2 2 2 2+S 2+S 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 2+S 2+S 3 3 1 1 2 1 2 Table 5-12. Logic Instructions -- High-Level Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A Operation Description Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Complement accumulator (A) Bytes 2 1 2 2 2 1 2 2 2 1 2 2 2 Cycles 2 1 2 2 2 1 2 2 2 1 2 2 2 Table 5-13. Arithmetic Instructions -- High-Level Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS INCS R RR R DA @HL RRb Operation Description Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Add 4-bit immediate data to A and skip on carry Add 8-bit immediate data to EA and skip on carry Add indirect data memory to A and skip on carry Add register pair (RR) contents to EA and skip on carry Add EA to register pair (RRb) and skip on carry Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 1 2 2 1 Cycles 1 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1+S 2+S 1+S 2+S 2+S 1+S Table 5-14. Bit Manipulation Instructions -- High-Level Summary Name BTST C DA.b mema.b memb.@L @H+DA.b BTSF DA.b mema.b memb.@L @H+DA.b BTSTZ mema.b memb.@L @H+DA.b BITS DA.b mema.b memb.@L @H+DA.b BITR DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L C,@H+DA.b BOR C,mema.b C,memb.@L C,@H+DA.b BXOR C,mema.b C,memb.@L C,@H+DA.b LDB mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load specified memory bit to carry bit Load specified indirect memory bit to carry bit Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Exclusive-OR carry with specified memory bit Logical-OR carry with specified memory bit Logical-AND carry flag with specified memory bit Clear specified memory bit to logic zero Set specified memory bit 2 2 Test specified bit; skip and clear if memory bit is set Test specified memory bit and skip if bit equals "0" Operand Operation Description Test specified bit and skip if carry flag is set Test specified bit and skip if memory bit is set Bytes 1 2 Cycles 1+S 2+S This section contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are experienced with the SAM47 instruction set. The same binary values and notation are also included in the detailed descriptions of individual instructions later in Section 5. If you are reading this user's manual for the first time, please just scan this very detailed information briefly. Most of the general information you will need to write application programs can be found in the high-level summary tables in the previous section. The following information is provided for each instruction: -- Instruction name -- Operand(s) -- Binary values -- Operation notation The tables in this section are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions Table 5-15. CPU Control Instructions -- Binary Code Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand . . 3 * . . . . . 5 3 * . . . . . 6 Binary Code . . . . . . . . . . . . . + . + . . . . . ( . ( . . . . . . . . . . . . Operation Notation C1 C 0 C IME 1 IME 0 PCON.2 1 PCON.3 1 No operation SMB n (n = 0, ... ,15) SRB n (n = 0, 1, 2, 3) PC13-0 memc.7-4, memc.3-0 < 1 ROM (2 x n) 5-4 PC13-12 ROM (2 x n) 3-0 PC11-8 ROM (2 x n + 1) 7-0 PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7) + ( . 7 8 ROM (2 x n) 7-6 EMB, ERB 5 6 + ( . Table 5-16. Program Control Instructions -- Binary Code Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR LJP ADR + . . . . . ( . . 5 . 5 . 5 5 5 5 . . . . . . . 6 . 6 . 6 . . . 6 . 6 6 Binary Code . . . . . . . . + + + + . . + + + . ( ( ( . . ( . ( . ( ( . . ( . ( ( . . . . . . . . . . . . . . . . . . . . 8 . 8 . Operation Notation Skip if R = im Skip if (HL) = im Skip if A = R Skip if A = (HL) Skip if A = (HL), E = (HL+1) Skip if EA = RR PC14-0 ADR14-0 + ( . 7 JP ADR . PC13-0 ADR13-0 + ( . 7 . 7 JPS JR ADR #im @WX @EA . . . 8 PC14-0 PC14-12 + ADR11-0 . . . . PC13-0 ADR (PC-15 to PC+16) PC13-0 PC13-8 + (WX) PC13-0 PC13-8 + (EA) [(SP-1) (SP-2)] EMB, ERB LCALL ADR + ( . 7 8 [(SP-3) (SP-4)] PC7-0 . [(SP-5) (SP-6)] PC14-8 CALL ADR . [(SP-1) (SP-2)] EMB, ERB + ( . 7 . 7 8 [(SP-3) (SP-4)] PC7-0 . [(SP-5) (SP-6)] PC13-8 8 [(SP-1) (SP-2)] EMB, ERB . [(SP-3) (SP-4)] PC7-0 CALLS ADR [(SP-5) (SP-6)] PC14-8 First Byte Condition ( ( . PC PC+2 to PC+16 . PC PC-1 to PC-15 JR #im . . . . . . . + + Table 5-16. Program Control Instructions -- Binary Code Summary (Continued) Name RET Operand - . Binary Code . . . Operation Notation PC14-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 5) (SP + 4) SP SP + 6 PC14-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) PSW (SP + 5) (SP + 4) SP SP + 6 PC14-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 5) (SP + 4) SP SP + 6 IRET - . . . SRET - . . . Table 5-17. Data Transfer Instructions -- Binary Code Summary Name XCH Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra . . . . . . . 5 5 . . . . 5 . 6 . 6 . . . . . 6 . . Binary Code . . . . . . . + + . . + + . ( ( ( ( ( . . . ( ( ( ( . . . . . . . . . . . . . . Operation Notation A DA A Ra A (RRa) A DA,E DA + 1 EA RRb A (HL), E (HL + 1) A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH A (RRa) A DA A Ra . A im . . . . Table 5-17. Data Transfer Instructions -- Binary Code Summary (Continued) Name LD Operand Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH A,@HL A,@HL EA,@WX EA,@EA A RR SB + . . . . . ( . 5 . 5 . . 5 5 . . . . . . . 6 . 6 . . . . . 6 . . . 6 . . . . . . . . . Binary Code . . . . . . . . . . . . . . . . . + + . + . + . . . . ( ( ( . ( ( . ( ( ( ( . . . . . ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Notation Ra im RR imm DA A Ra A A (HL), E (HL + 1) A DA, E DA + 1 EA RRb (HL) A DA A, DA + 1 E RRb EA (HL) A, (HL + 1) E A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH EA [PC14-8 + (WX)] EA [PC14-8 + (EA)] C A.0, A3 C A.n-1 A.n (n = 1, 2, 3) ((SP-1)) ((SP-2)) (RR), (SP) (SP)-2 ((SP-1)) (SMB), ((SP-2)) (SRB), (SP) (SP)-2 Table 5-17. Data Transfer Instructions -- Binary Code Summary (Concluded) Name POP Operand RR SB . . . . Binary Code . . . ( . . . Operation Notation RR (SP), RR (SP + 1) SP SP + 2 (SRB) (SP), SMB (SP + 1), SP SP + 2 Table 5-18. Logic Instructions -- Binary Code Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary Code . . . + . + . + . . ( . ( ( ( . ( ( ( . ( ( . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Notation A A AND im A A AND (HL) EA EA AND RR RRb RRb AND EA A A OR im A A OR (HL) EA EA OR RR RRb RRb OR EA A A XOR im A A XOR (HL) EA EA XOR (RR) RRb RRb XOR EA A Table 5-19. Arithmetic Instructions -- Binary Code Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS R RR INCS R DA @HL RRb . . . . . . . . . . . 5 . . . . . . . 5 . . . . 6 . . . . . . . . . . . . . . . 6 . . Binary Code . . . . . . . . . . . + + . . . + . . ( ( ( . ( ( ( ( ( ( ( ( ( ( . ( . ( . . . . . . . . . . . . . . . . . . Operation Notation C, A A + (HL) + C C, EA EA + RR + C C, RRb RRb + EA + C . A A + im; skip on carry . . . . . . . . . . . . . . . . . . . . . . EA EA + imm; skip on carry A A+ (HL); skip on carry EA EA + RR; skip on carry RRb RRb + EA; skip on carry C,A A-(HL)-C C, EA EA-RR-C C,RRb RRb-EA-C A A-(HL); skip on borrow EA EA-RR; skip on borrow RRb RRb-EA; skip on borrow R R-1; skip on borrow RR RR-1; skip on borrow R R+1; skip on carry DA DA+1; skip on carry (HL) (HL)+1; skip on carry RRb RRb+1; skip on carry Table 5-20. Bit Manipulation Instructions -- Binary Code Summary Name BTST C DA.b mema.b memb.@L @H+DA.b BTSF DA.b mema.b memb.@L @H+DA.b BTSTZ mema.b memb.@L Operand . . . . . 5 . 5 . . 5 . . 6 . 6 . . 6 . Binary Code . . . . . . . . . . . . . + 6 + . + 6 + 6 + . + 6 + . ( . . . ( . ( . . . ( ( . ( ( . . + . . . + . . . + . . + . ( . . . . . ( . . ( . . ( . Operation Notation Skip if C = 1 Skip if DA.b = 1 Skip if mema.b = 1 Skip if [memb.7-2 + L.3-2].[L.1-0] = 1 Skip if [H + DA.3-0].b = 1 Skip if DA.b = 0 Skip if mema.b = 0 Skip if [memb.7-2 + L.3-2].[L.1-0] = 0 Skip if [H + DA.3-0].b = 0 Skip if mema.b = 1 and clear Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear Skip if [H + DA.3-0].b =1 and clear DA.b 1 mema.b 1 [memb.7-2 + L.3-2].[L.1-0] 1 [H + DA.3-0].b 1 @H+DA.b BITS DA.b mema.b memb.@L @H+DA.b . . . Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Continued) Name BITR Operand DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L . . . 5 . . . . Binary Code 6 . . . . . . . . . . . . . . + 6 + . . 6 . + . . 6 . + . . 6 . + . ( ( ( ( ( . + . . + . + + . . . . ( . . ( . . . ( . . ( . Operation Notation DA.b 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 [H + DA.3-0].b 0 C C AND mema.b C C AND [memb.7-2 + L.3-2]. [L.1-0] C C AND [H + DA.3-0].b C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] C C OR [H + DA.3-0].b C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] C C XOR [H + DA.3-0].b C,@H+DA.b BOR C,mema.b C,memb.@L . . C,@H+DA.b BXOR C,mema.b C,memb.@L . . C,@H+DA.b . Second Byte Bit Addresses ( ( . FB0H-FBFH . FF0H-FFFH mema.b . . + . + Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Concluded) Name LDB Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b . . . . . . . . Binary Code . . 6 . . 6 . ( ( . . + . . . + . . . ( . . . . ( . . Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C H+[DA.3-0].b (C) C mema.b C memb.7-2+[L.3-2]. [L.1-0] C [H + DA.3-0].b . + . + Second Byte Bit Addresses ( ( . . mema.b . . + . + FB0H-FBFH FF0H-FFFH This section contains detailed information and programming examples for each instruction of the SAM47 instruction set. Information is arranged in a consistent format to improve readability and for use as a quickreference resource for application programmers. If you are reading this user's manual for the first time, please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set. The information elements of the instruction description format are as follows: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Operation overview (from the "High-Level Summary" table) -- Textual description of the instruction's effect -- Binary code overview (from the "Binary Code Summary" table) -- Programming example(s) to show how the instruction is used ADC Operation: dst,src !!" Operand A,@HL EA,RR RRb,EA Operation Summary Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2 Description: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is cleared. If 'ADC A,@HL' is followed by an 'ADS A,#im' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. (This condition is valid only for 'ADC A,@HL' instructions. If an overflow occurs following an 'ADS A,#im' instruction, the next instruction will not be skipped.) Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 1 0 r1 0 r1 0 0 0 0 0 C, RRb RRb + EA + C Operation Notation C, A A + (HL) + C C, EA EA + RR + C Examples: 1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF ADC JPS EA,HL XXX ; C "1" ; EA 0C3H + 0AAH + 1H = 6EH, C "1" ; Jump to XXX;no skip after ADC 2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF ADC JPS EA,HL XXX ; C "0" ; EA 0C3H + 0AAH + 0H = 6DH, C "1" ; Jump to XXX; no skip after ADC ADC Examples: !!" (Continued) 3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction immediately after the ADS. An ADS instruction immediately after the ADC does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS A,#8H A,#6H A,@HL A,#0AH XXX ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A 0EH + 9H + C(0), C "1" Skip this instruction because C = "1" after ADC result b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS JPS A,#3H A,#6H A,@HL A,#0AH XXX ; ; ; ; ; ; ; C "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.) #$%&'!()% ADS Operation: dst,src Operand A, #im EA, #imm A,@HL EA,RR RRb, EA Operation Summary Add 4-bit immediate data to A and skip on overflow Add 8-bit immediate data to EA and skip on overflow Add indirect data memory to A and skip on overflow Add register pair (RR) contents to EA and skip on overflow Add EA to register pair (RRb) and skip on overflow Bytes 1 2 1 2 2 Cycles 1+S 2+S 1+S 2+S 2+S Description: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. If 'ADS A,#im' follows an 'ADC A,@HL' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. This skip condition is valid only for 'ADC A,@HL' instructions, however. If an overflow occurs following an ADS instruction, the next instruction is not skipped. Operand A, #im EA,#imm A,@HL EA,RR RRb,EA 1 1 d7 0 1 1 1 1 0 1 d6 0 1 0 1 0 1 0 d5 1 0 0 0 0 Binary Code 0 0 d4 1 1 1 1 1 d3 1 d3 1 1 1 1 0 d2 0 d2 1 1 r2 1 r2 d1 0 d1 1 0 r1 0 r1 d0 1 d0 1 0 0 0 0 RRb RRb + EA; skip on overflow A A + (HL); skip on overflow EA EA + RR; skip on overflow Operation Notation A A + im; skip on overflow EA EA + imm; skip on overflow Examples: 1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag = "0": ADS JPS JPS EA,HL XXX YYY ; ; ; ; ; EA 0C3H + 0AAH = 6DH ADS skips on overflow, but carry flag value is not affected. This instruction is skipped since ADS had an overflow. Jump to YYY. #$%&'!()% ADS Examples: (Continued) 2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and the carry flag = "0": ADS JPS EA,HL XXX ; EA 0C3H + 12H = 0D5H ; Jump to XXX; no skip after ADS. 3. If 'ADC A,@HL' is followed by an 'ADS A,#im', the ADC skips on overflow to the instruction mmediately after the ADS. An 'ADS A,#im' instruction immediately after the 'ADC A,@HL' does not skip even if overflow occurs. This function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS A,#8H A,#6H A,@HL A,#0AH XXX ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A 0EH + 9H + C(0) = 7H, C "1" Skip this instruction because C = "1" after ADC result. b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS JPS A,#3H A,#6H A,@HL A,#0AH XXX ; ; ; ; ; ; ; C "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH, C "0" No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.) %*+) AND Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Bytes 2 1 2 2 Cycles 2 1 2 2 Description: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The logical AND operation results in a "1" whenever the corresponding bits in the two operands are both "1"; otherwise a "0" is stored in the corresponding destination bit. The contents of the source are unaffected. Operand A,#im A,@HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 0 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb AND EA A A AND (HL) EA EA AND RR Operation Notation A A AND im Example: If the extended accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction AND EA,HL leaves the value 41H (01000001B) in the extended accumulator EA . %*+) BAND Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-AND carry flag with memory bit Bytes 2 2 2 Cycles 2 2 2 Description: The specified bit of the source is logically ANDed with the carry flag bit value. If the Boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. The bit value of the source operand is not affected. Operand C,mema.b C,memb.@L 1 1 0 C,@H+DA.b 1 0 1 1 1 1 0 1 1 0 1 b1 Binary Code 1 1 0 1 b0 0 0 a5 0 a3 1 1 a4 1 a2 0 0 a3 0 a1 1 1 a2 1 a0 C C AND [H + DA.3-0].b Operation Notation C C AND mema.b C C AND [memb.7-2 + L.3-2]. [L.1-0] Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. The following instructions set the carry flag if P1.0 (port 1.0) is equal to "1" (and assuming the carry flag is already set to "1"): SMB BAND 15 C,P1.0 ; C "1" ; If P1.0 = "1", C "1" ; If P1.0 = "0", C "0" 2. Assume the P1 address is FF1H and the value for register L is 5H (0101B). The address (memb.7-2) is 111100B; (L.3-2) is 01B. The resulting address is 11110001B or FF1H, specifying P1. The bit value for the BAND instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P1.1: LD BAND L,#5H C,P1.@L ; P1.@L is specified as P1.1 ; C AND P1.1 %*+) BAND Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BAND instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BAND EQU 20H.3 H,#2H C,@H+FLAG ; C AND FLAG (20H.3) ',' BITR Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Clear specified memory bit to logic zero Bytes 2 2 2 2 Cycles 2 2 2 2 Description: A BITR instruction clears to logic zero (resets) the specified bit within the destination operand. No other bits in the destination are affected. Operand DA.b mema.b memb.@L @H+DA.b 1 a7 1 1 0 1 0 1 a6 1 1 1 1 0 b1 a5 1 1 0 1 b1 Binary Code b0 a4 1 1 0 1 b0 0 a3 1 1 a5 1 a3 0 a2 1 1 a4 1 a2 0 a1 1 1 a3 1 a1 0 a0 0 0 a2 0 a0 [H + DA.3-0].b 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 Operation Notation DA.b 0 Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. If the Bit location 30H.2 in the RAM has a current value of "1". The following instruction clears the third bit of location 30H to "0": BITR 30H.2 ; 30H.2 "0" 2. You can use BITR in the same way to manipulate a port address bit: BITR P0.0 ; P0.0 "0" ',' BITR Examples: (Continued) 3. For clearing P0.2, P0.3, and P1.0-P1.3 to "0": BP2 LD BITR INCS CPSE JR L,#2H P0.@L L L,#8H BP2 ; First, P0.@2H = P0.2 ; (111100B) + 00B.10B = 0F0H.2 4. If bank 0, location 0A0H.0 is cleared (and regardless of whether the EMB value is logic zero), BITR has the following effect: FLAG EQU 0A0H.0 BITR EMB LD BITR H,#0AH @H+FLAG ; Bank 0 (AH + 0H).0 = 0A0H.0 "0" *2 $ 9 ' BITS Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Set specified memory bit Bytes 2 2 2 2 Cycles 2 2 2 2 Description: This instruction sets the specified bit within the destination without affecting any other bits in the destination. BITS can manipulate any bit that is addressable using direct or indirect addressing modes. Operand DA.b mema.b memb.@L @H+DA.b 1 a7 1 1 0 1 0 1 a6 1 1 1 1 0 b1 a5 1 1 0 1 b1 Binary Code b0 a4 1 1 0 1 b0 0 a3 1 1 a5 1 a3 0 a2 1 1 a4 1 a2 0 a1 1 1 a3 1 a1 1 a0 1 1 a2 1 a0 [H + DA.3-0].b 1 mema.b 1 [memb.7-2 + L.3-2].b [L.1-0] 1 Operation Notation DA.b 1 Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. If the bit location 30H.2 in the RAM has a current value of "0", the following instruction sets the second bit of location 30H to "1". BITS 30H.2 ; 30H.2 "1" 2. You can use BITS in the same way to manipulate a port address bit: BITS P0.0 ; P0.0 "1" ' BITS Examples: (Continued) 3. For setting P0.2, P0.3, and P1.0-P1.3 to "1": BP2 LD BITS INCS CPSE JR L,#2H P0.@L L L,#8H BP2 ; First, P0.@02H = P0.2 ; (111100B) + 00B.10B = 0F0H.2 4. If bank 0, location 0A0H.0, is set to "1" and the EMB = "0", BITS has the following effect: FLAG EQU 0A0H.0 BITR EMB LD BITS H,#0AH @H+FLAG ; Bank 0 (AH + 0H).0 = 0A0H.0 "1" *2 $ 9 %*+) BOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-OR carry with specified memory bit Bytes 2 2 2 Cycles 2 2 2 Description: The specified bit of the source is logically ORed with the carry flag bit value. The value of the source is unaffected. Operand C,mema.b C,memb.@L 1 1 0 C,@H+DA.b 1 0 1 1 1 1 0 1 1 0 1 b1 Binary Code 1 1 0 1 b0 0 0 a5 0 a3 1 1 a4 1 a2 1 1 a3 1 a1 0 0 a2 0 a0 C C OR [H + DA.3-0].b Operation Notation C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. The carry flag is logically ORed with the P1.0 value: RCF BOR C,P1.0 ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0" 2. The P1 address is FF1H and register L contains the value 1H (0001B). The address (memb.72) is 111100B and (L.3-2) = 00B. The resulting address is 11110000B or FF0H, specifying P0. The bit value for the BOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P0.1: LD BOR L,#1H C,P1.@L ; P1.@L is specified as P0.1; C OR P0.1 %*+) BOR Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BOR EQU 20H.3 H,#2H C,@H+FLAG ; C OR FLAG (20H.3) ',#$% ),' BTSF Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Test specified memory bit and skip if bit equals "0" Bytes 2 2 2 2 Cycles 2+S 2+S 2+S 2+S Description: The specified bit within the destination operand is tested. If it is a "0", the BTSF instruction skips the instruction which immediately follows it; otherwise the instruction following the BTSF is executed. The destination bit value is not affected. Operand DA.b mema.b memb.@L 1 a7 1 1 0 @H + DA.b 1 0 1 a6 1 1 1 1 0 b1 a5 1 1 0 1 b1 Binary Code b0 a4 1 1 0 1 b0 0 a3 1 1 a5 1 a3 0 a2 0 0 a4 0 a2 1 a1 0 0 a3 0 a1 0 a0 0 0 a2 0 a0 Skip if [H + DA.3-0].b = 0 Skip if mema.b = 0 Skip if [memb.7-2 + L.3-2]. [L.1-0] = 0 Operation Notation Skip if DA.b = 0 Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FF0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. If RAM bit location 30H.2 is set to "0", the following instruction sequence will cause program to continue execution from the instruction identifed as LABEL2: BTSF RET JP 30H.2 LABEL2 ; If 30H.2 = "0", then skip ; If 30H.2 = "1", return the 2. You can use BTSF in the same way to test a port pin address bit: BTSF RET JP P1.0 LABEL3 ; If P1.0 = "0", then skip ; If P1.0 = "1", then return ',#$% ),' BTSF Examples: (Continued) 3. P0.2, P0.3 and P1.0-P1.3 are tested: BP2 LD BTSF RET INCS CPSE JR L,#2H P0.@L L L,#8H BP2 ; First, P1.@02H = P0.2 ; (111100B) + 00B.10B = 0F0H.2 4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTSF has the following effect: FLAG EQU 0A0H.0 BITR EMB LD BTSF RET H,#0AH @H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "0", then skip ',#$% !-' BTST Operation: C DA.b mema.b memb.@L @H+DA.b dst.b Operand Operation Summary Test carry bit and skip if set (= "1") Test specified bit and skip if memory bit is set Bytes 1 2 2 2 2 Cycles 1+S 2+S 2+S 2+S 2+S Description: The specified bit within the destination operand is tested. If it is "1", the instruction that immediately follows the BTST instruction is skipped; otherwise the instruction following the BTST instruction is executed. The destination bit value is not affected. Operand C DA.b mema.b memb.@L 1 1 a7 1 1 0 @H+DA.b 1 0 1 1 a6 1 1 1 1 0 0 b1 a5 1 1 0 1 b1 Binary Code 1 b0 a4 1 1 0 1 b0 0 0 a3 1 1 a5 1 a3 1 0 a2 0 0 a4 0 a2 1 1 a1 0 0 a3 0 a1 1 1 a0 1 1 a2 1 a0 Skip if [H + DA.3-0].b = 1 Skip if mema.b = 1 Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 Operation Notation Skip if C = 1 Skip if DA.b = 1 Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. If RAM bit location 30H.2 is set to "0", the following instruction sequence will execute the RET instruction: BTST RET JP 30H.2 LABEL2 ; If 30H.2 = "1", then skip ; If 30H.2 = "0", return ',#$% !-' BTST Examples: (Continued) 2. You can use BTST in the same way to test a port pin address bit: BTST RET JP P1.0 LABEL3 ; If P1.0 = "1", then skip ; If P1.0 = "0", then return 3. P0.2, P0.3 and P1.0-P1.3 are tested: BP2 LD BTST RET INCS CPSE JR L,#2H P0.@L L L,#8H BP2 ; First, P0.@02H = P0.2 ; (111100B) + 00B.10B = 0F0H.2 4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTST has the following effect: FLAG EQU 0A0H.0 BITR EMB LD BTST RET H,#0AH @H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", then skip ',#$% !-'. )'! BTSTZ Operation: dst.b Operand mema.b memb.@L @H+DA.b Operation Summary Test specified bit; skip and clear if memory bit is set Bytes 2 2 2 Cycles 2+S 2+S 2+S Description: The specified bit within the destination operand is tested. If it is a "1", the instruction immediately following the BTSTZ instruction is skipped; otherwise the instruction following the BTSTZ is executed. The destination bit value is cleared. Operand mema.b memb.@L 1 1 0 @H+DA.b 1 0 1 1 1 1 0 1 1 0 1 b1 Binary Code 1 1 0 1 b0 1 1 a5 1 a3 1 1 a4 1 a2 0 0 a3 0 a1 1 1 a2 1 a0 Skip if [H + DA.3-0].b =1 and clear Operation Notation Skip if mema.b = 1 and clear Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. Port pin P0.0 is toggled by checking the P0.0 value (level): BTSTZ BITS JP P0.0 P0.0 LABEL3 ; If P0.0 = "1", then P0.0 "0" and skip ; If P0.0 = "0", then P0.0 "1" 2. For toggling P2.2, P2.3, and P3.0-P3.3: BP2 LD BTSTZ BITS INCS JR L,#0AH P2.@L P2.@L L BP2 ; First, P2.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2 ',#$% !-'. )'! BTSTZ Examples: (Continued) 3. Bank 0, location 0A0H.0, is tested and EMB = "0": FLAG EQU 0A0H.0 BITR EMB LD BTSTZ BITS H,#0AH @H+FLAG @H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", clear and skip ; If 0A0H.0 = "0", then 0A0H.0 "1" /+)-,&' BXOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Exclusive-OR carry with memory bit Bytes 2 2 2 Cycles 2 2 2 Description: The specified bit of the source is logically XORed with the carry bit value. The resultant bit is written to the carry flag. The source value is unaffected. Operand C,mema.b C,memb.@L 1 1 0 C,@H+DA.b 1 0 1 1 1 1 0 1 1 0 1 b1 Binary Code 1 1 0 1 b0 0 0 a5 0 a3 1 1 a4 1 a2 1 1 a3 1 a1 1 1 a2 1 a0 C C XOR [H + DA.3-0].b Operation Notation C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 Examples: 1. The carry flag is logically XORed with the P1.0 value: RCF BXOR C,P1.0 ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0" 2. The P1 address is FF1H and register L contains the value 1H (0001B). The address (memb.72) is 111100B and (L.3-2) = 00B. The resulting address is 11110000B or FF0H, specifying P0. The bit value for the BXOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P0.1: LD BXOR L,#0001B C,P0.@L ; P1.@L is specified as P0.1; C XOR P0.1 /+)-,&' BXOR (Continued) Examples: 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BXOR EQU 20H.3 H,#2H C,@H+FLAG ; C XOR FLAG (20H.3) ))!%+'-!' CALL Operation: dst Operand ADR Operation Summary Call direct in page (14 bits) Bytes 3 Cycles 4 Description: CALL calls a subroutine located at the destination address. The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decreasing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 16 K byte program memory address space. Operand ADR 1 0 a7 1 1 a6 0 a5 Binary Code 1 a4 1 a3 0 a2 1 a9 a1 1 a8 a0 a13 a12 a11 a10 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8 Example: The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0E3FH. Executing the instruction CALL PLAY at location 0123H will generate the following values: SP = 0FFH = 0FEH = 0FDH = 0FCH = 0FBH = 0FAH = PC = 0FAH 0H EMB, ERB 2H 3H 0H 1H 0E3FH Data is written to stack locations 0FFH-0FAH as follows: SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP (0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (00H) 0 0 0 PC11 - PC8 0 PC13 PC12 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0 ))!%+'-!'0 CALLS Operation: dst Operand ADR %!1 Operation Summary Call direct in page (11 bits) Bytes 2 Cycles 3 Description: The CALLS instruction unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction. Then, it pushes the result onto the stack, decreasing the stack pointer six times. The higher bits of the PC, with the exception of the lower 11 bits, are cleared. The CALLS instruction can be used in the all range (0000H-7FFFH), but the subroutine call must therefore be located within the 2 K byte block (0000H-07FFH) of program memory. Operand ADR 1 a7 1 a6 1 a5 Binary Code 0 a4 1 a3 a10 a2 a9 a1 a8 a0 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC14-8 Example: The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0345H. Executing the instruction CALLS PLAY at location 0123H will generate the following values: SP = 0FFH = 0FEH = 0FDH = 0FCH = 0FBH = 0FAH = PC = 0FAH 0H EMB, ERB 2H 3H 0H 1H 0345H Data is written to stack locations 0FFH-0FAH as follows: SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP (0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (00H) 0 0 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0 %2$)'2' !!" )* CCF Operation: Operand Operation Summary Complement carry flag Bytes 1 Cycles 1 Description: The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa. Operand 1 1 0 Binary Code 1 0 1 1 0 C Operation Notation Example: If the carry flag is logic zero, the instruction CCF changes the value to logic one. %2$)'2'++-2-)%! COM Operation: A Operand A Operation Summary Complement accumulator (A) Bytes 2 Cycles 2 Description: The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice versa. Operand A 1 0 1 0 0 1 Binary Code 1 1 1 1 1 1 0 1 1 1 A Operation Notation Example: If the accumulator contains the value 4H (0100B), the instruction COM A leaves the value 0BH (1011B) in the accumulator. %2$!'#$(3-) CPSE Operation: dst,src Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR Operation Summary Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Bytes 2 2 2 1 2 2 Cycles 2+S 2+S 2+S 1+S 2+S 2+S Description: CPSE compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. Neither operand is affected by the comparison. Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR 1 d3 1 0 1 0 0 1 0 1 1 1 d2 1 1 1 1 0 1 0 1 1 0 d1 0 1 0 1 1 0 0 0 1 Binary Code 1 d0 1 1 1 0 1 1 0 1 0 1 0 1 d3 1 1 1 1 1 1 1 0 r2 1 d2 1 r2 0 1 0 1 r2 0 r1 0 d1 0 r1 0 0 0 0 r1 1 r0 1 d0 1 r0 0 0 1 0 0 Skip if EA = RR Skip if A = (HL) Skip if A = (HL), E = (HL+1) Skip if A = R Skip if (HL) = im Operation Notation Skip if R = im Example: The extended accumulator contains the value 34H and register pair HL contains 56H. The second instruction (RET) in the instruction sequence CPSE RET EA,HL is not skipped. That is, the subroutine returns since the result of the comparison is 'not equal.' '+!'2'#$%%!!% DECS Operation: dst Operand R RR Operation Summary Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Bytes 1 2 Cycles 1+S 2+S Description: The destination is decremented by one. An original value of 00H will underflow to 0FFH. If a borrow occurs, a skip is executed. The carry flag value is unaffected. Operand R RR 0 1 1 1 1 1 0 0 0 Binary Code 0 1 1 1 1 1 r2 1 r2 r1 0 r1 r0 0 0 Operation Notation R R-1; skip on borrow RR RR-1; skip on borrow Examples: 1. Register pair HL contains the value 7FH (01111111B). The following instruction leaves the value 7EH in register pair HL: DECS HL 2. Register A contains the value 0H. The following instruction sequence leaves the value 0FFH in register A. Since a "borrow" occurs, the 'CALL PLAY1' instruction is skipped and the 'CALL PLAY2' instruction is executed: DECS CALL CALL A PLAY1 PLAY2 ; "Borrow" occurs ; Skipped ; Executed ,4)''!!-$, DI Operation: Operand Operation Summary Disable all interrupts Bytes 2 Cycles 2 Description: Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts. Interrupts can still set their respective interrupt status latches, but the CPU will not directly service them. Operand 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 0 0 Operation Notation IME 0 Example: If the IME bit (bit 3 of the IPR) is logic one (e.g., all instructions are enabled), the instruction DI sets the IME bit to logic zero, disabling all interrupts. 4)''!!-$, EI Operation: Operand Operation Summary Enable all interrupts Bytes 2 Cycles 2 Description: Bit 3 of the interrupt priority register IPR (IME) is set to logic one. This allows all interrupts to be serviced when they occur, assuming they are enabled. If an interrupt's status latch was previously enabled by an interrupt, this interrupt can also be serviced. Operand 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 0 IM 1 Operation Notation Example: If the IME bit (bit 3 of the IPR) is logic zero (e.g., all instructions are disabled), the instruction EI sets the IME bit to logic one, enabling all interrupts. )'$'!% IDLE Operation: Operand Operation Summary Engage CPU idle mode Bytes 2 Cycles 2 Description: IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (PCON). After an IDLE instruction has been executed, peripheral hardware remains operative. In application programs, an IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after IDLE instruction, leakage current could be flown because of the floating state in the internal bus. Operand 1 1 1 0 1 1 Binary Code 1 0 1 0 1 0 1 1 1 1 Operation Notation PCON.2 1 Example: The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one, stopping the CPU clock. The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed. +!'2'#$% !!" INCS Operation: R DA @HL RRb dst Operand Operation Summary Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 Cycles 1+S 2+S 2+S 1+S Description: The instruction INCS increments the value of the destination operand by one. An original value of 0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The carry flag value is unaffected. Operand R DA @HL RRb 0 1 a7 1 0 1 1 1 a6 1 1 0 0 0 a5 0 1 0 Binary Code 1 0 a4 1 0 0 1 1 a3 1 0 0 r2 0 a2 1 0 r2 r1 1 a1 0 1 r1 r0 0 a0 1 0 0 RRb RRb + 1; skip on carry (HL) (HL) + 1; skip on carry Operation Notation R R + 1; skip on carry DA DA + 1; skip on carry Example: Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The instruction sequence INCS INCS INCS @HL HL @HL ; 7EH "0" ; Skip ; 7EH "1" leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Since a carry occurred, the second instruction is skipped. The carry flag value remains unchanged. '-!(!%2'!!-$ IRET Operation: Operand Operation Summary Return from interrupt Bytes 1 Cycles 3 Description: IRET is used at the end of an interrupt service routine. It pops the PC values successively from the stack and restores them to the program counter. The stack pointer is incremented by six and the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also automatically restored to their pre-interrupt values. Program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower-level or same-level interrupt was pending when the IRET was executed, IRET will be executed before the pending interrupt is processed. Since the 15th bit of an interrupt start address is not loaded in the PC when the interrupt is occured, this bit of PC values is always interpreted as a logic zero at that time. The start address of an interrupt in the ROM must for this reason be located in 0000H-3FFFH. Operand 1 1 0 Binary Code 1 0 1 0 1 Operation Notation PC14-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) PSW (SP + 5) (SP + 4) SP SP + 6 Example: The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location 0123H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively. The instruction IRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0123H. During a return from interrupt, data is popped from the stack to the program counter. The data in stack locations 0FFH-0FAH is organized as follows: SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 (0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (00H) IS1 C 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 IS0 SC2 EMB SC1 ERB SC0 5-2$ JP Operation: dst Operand ADR Operation Summary Jump to direct address (14 bits) Bytes 3 Cycles 3 Description: JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. The destination can be anywhere in the 16 K byte program memory address space. Operand ADR 1 0 a7 1 0 a6 0 a5 Binary Code 1 a4 1 a3 0 a2 1 a9 a1 1 a8 a0 a13 a12 a11 a10 Operation Notation PC13-0 ADR13-0 Example: The label 'SYSCON' is assigned to the instruction at program location 07FFH. The instruction JP SYSCON at location 0123H will load the program counter with the value 07FFH. 5-2$0 JPS Operation: dst %!1 Operand ADR Operation Summary Jump direct in page (12 bits) Bytes 2 Cycles 2 Description: JPS causes an unconditional branch to the indicated address with the 4 K byte program memory address space. Bits 0-11 of the program counter are replaced with the directly specified address. The destination address for this jump is specified to the assembler by a label or by an actual address in program memory. Operand ADR 1 a7 0 a6 0 a5 Binary Code 1 a4 a11 a10 a3 a2 a9 a1 a8 a0 Operation Notation PC14-0 PC14-12+ADR11-0 Example: The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction JPS SUB at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS instruction jumps to the address in the block in which the instruction is located. If the first byte of the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or 0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program malfunction. 5-2$')&'0'!" JR Operation: dst Operand #im @WX @EA %!1 Operation Summary Branch to relative immediate address Branch relative to contents of WX register Branch relative to contents of EA Bytes 1 2 2 Cycles 2 3 3 Description: JR causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC. The range of the relative address is current PC - 15 to current PC + 16. The destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (-). For immediate addressing, the (+) range is from 2 to 16 and the (-) range is from -1 to -15. If a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. For JR @WX and JR @EA branch relative instructions, the valid range for the relative address is 0H-0FFH. The destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. Normally, the 'JR @WX' and 'JR @EA' instructions jump to the address in the page in which the instruction is located. However, if the first byte of the instruction code is located at address xxFEH or xxFFH, the instruction will jump to the next page. Operand #im @WX @EA 1 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 PC14-0 PC14-8 + (EA) Binary Code Operation Notation PC14-0 ADR (PC-15 to PC+16) PC14-0 PC14-8 + (WX) First Byte Condition a2 a2 a1 a1 a0 a0 PC PC+2 to PC+16 PC PC-1 to PC-15 JR #im 0 0 0 0 0 0 1 0 a3 a3 5-2$')&'0'!" JR Examples: (Continued) %!1 1. A short form for a relative jump to label 'KK' is the instruction JR KK where 'KK' must be within the allowed range of current PC-15 to current PC+16. The JR instruction has in this case the effect of an unconditional JP instruction. 2. In the following instruction sequence, if the instruction 'LD WX, #02H' were to be executed in place of 'LD WX,#00H', the program would jump to 1004H and 'JPS CCC' would be executed. If 'LD WX,#03H' were to be executed, the jump would be to1006H and 'JPS DDD' would be executed. ORG JPS JPS JPS JPS LD LD ADS JR 1000H AAA BBB CCC DDD WX,#00H ; WX 00H EA,WX WX,EA ; WX (WX) + (EA) @WX ; Current PC12-8 (10H) + WX (00H) = 1000H ; Jump to address 1000H and execute JPS AAA XXX 3. Here is another example: ORG LD LD LD LD LD JPS LD EA,#00H JR 1100H A,#0H A,#1H A,#2H A,#3H 30H,A YYY @EA ; Address 30H A ; EA 00H ; Jump to address 1100H ; Address 30H 00H XXX If 'LD EA,#01H' were to be executed in place of 'LD EA,#00H', the program would jump to 1101H and address 30H would contain the value 1H. If 'LD EA,#02H' were to be executed, the jump would be to 1102H and address 30H would contain the value 2H. ))!%+'-!' CALL Operation: dst Operand ADR15 Operation Summary Call direct in page (15 bits) Bytes 3 Cycles 4 Description: CALL calls a subroutine located at the destination address. The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decrementing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 32-Kbyte program memory address space. The LCALL instruction can be used in the all range (0000H-7FFFH) while the CALL instruction can be used in the only range (0000H-3FFFH). Operand ADR15 1 0 a7 1 a6 0 a5 Binary Code 1 a4 1 a3 0 a2 1 a9 a1 0 a8 a0 a14 a13 a12 a11 a10 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC14-8 Example: The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 5E3FH. Executing the instruction LCALL PLAY at location 0123H will generate the following values: SP = 0FFH = 0FEH = 0FDH = 0FCH = 0FBH = 0FAH = PC = 0FAH 0H EMB, ERB 2H 3H 0H 1H 5E3FH Data is written to stack locations 0FFH-0FAH as follows: 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH 0 0 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0 % LD Operation: dst,src Operand A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA Operation Summary Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Bytes 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 Cycles 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 Description: The contents of the source are loaded into the destination. The source's contents are unaffected. If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two times in succession, only the first LD will be executed; the other similar instructions that immediately follow the first LD will be treated like a NOP. This is called the 'redundancy effect' (see examples below). Operand A,#im A,@RRa A,DA A,Ra Ra,#im 1 1 1 a7 1 0 1 d3 0 0 0 a6 1 0 1 d2 1 0 0 a5 0 0 0 d1 Binary Code 1 0 0 a4 1 0 1 d0 d3 1 1 a3 1 1 1 1 d2 i2 1 a2 1 r2 0 r2 d1 i1 0 a1 0 r1 0 r1 d0 i0 0 a0 1 r0 1 r0 Ra im A Ra A im A (RRa) A DA Operation Notation % LD Description: (Continued) Operand RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA 1 d7 1 a7 1 0 1 0 1 a7 1 1 1 1 a7 1 1 1 0 0 d6 0 a6 1 0 1 0 1 a6 1 1 1 1 a6 1 1 1 0 0 d5 0 a5 0 0 0 0 0 a5 0 1 0 0 a5 0 1 0 0 Binary Code 0 d4 0 a4 1 0 1 0 0 a4 1 1 0 0 a4 1 1 1 0 0 d3 1 a3 1 0 1 1 1 a3 1 0 0 1 a3 1 0 1 0 r2 d2 0 a2 1 r2 1 0 1 a2 1 r2 1 1 a2 1 r2 1 0 r1 d1 0 a1 0 r1 0 0 1 a1 0 r1 0 0 a1 0 r1 0 0 1 d0 1 a0 1 r0 0 0 0 a0 0 0 0 1 a0 0 0 0 0 (HL) A, (HL + 1) E RRb EA (HL) A DA A, DA + 1 E EA RRb A DA, E DA + 1 A (HL), E (HL + 1) Ra A DA A Operation Notation RR imm Examples: 1. RAM location 30H contains the value 4H. The RAM location values are 40H, 41H and 0AH, 3H respectively. The following instruction sequence leaves the value 40H in point pair HL, 0AH in the accumulator and in RAM location 40H, and 3H in register E. LD LD LD LD LD HL,#30H A,@HL HL,#40H EA,@HL @HL,A ; ; ; ; ; HL 30H A 4H HL 40H A 0AH, E 3H RAM (40H) 0AH % LD Examples: (Continued) 2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two times in succession, only the first LD is executed; the next instructions are treated as NOPs. Here are two examples of this 'redundancy effect': LD LD LD LD LD LD LD LD LD A,#1H EA,#2H A,#3H 23H,A HL,#10H HL,#20H A,#3H EA,#35 @HL,A ; ; ; ; ; ; ; ; ; A 1H NOP NOP (23H) 1H HL 10H NOP A 3H NOP (10H) 3H The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes: Instruction LD A,#im Operation Description and Guidelines Since the 'redundancy effect' occurs with instructions like LD EA,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like NOPs. Load the data memory contents pointed to by 8-bit RRa register pairs (HL, WX, WL) to the A register. Load direct data memory contents to the A register. Load 4-bit register Ra (E, L, H, X, W, Z, Y) to the A register. Load 4-bit immediate data into the Ra register (E, L, H, X, W, Y, Z). LD A,@RRa LD A,DA LD A,Ra LD Ra,#im LD RR,#imm Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a redundancy effect if the operation addresses the HL or EA registers. LD DA,A LD Ra,A Load contents of register A to direct data memory address. Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y). % LD Examples: (Concluded) Instruction LD EA,@HL Operation Description and Guidelines Load data memory contents pointed to by 8-bit register HL to the A register, and the contents of HL+1 to the E register. The contents of register L must be an even number. If the number is odd, the LSB of register L is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to HL and the next instruction 'LD EA,@HL' loads the contents of 36H to register A and the contents of 37H to register E. Load direct data memory contents of DA to the A register, and the next direct data memory contents of DA + 1 to the E register. The DA value must be an even number. If it is an odd number, the LSB of DA is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD EA,37H' loads the contents of 36H to the A register and the contents of 37H to the E register. Load 8-bit RRb register (HL, WX, YZ) to the EA register. H, W, and Y register values are loaded into the E register, and the L, X, and Z values into the A register. Load A register contents to data memory location pointed to by the 8-bit HL register value. Load the A register contents to direct data memory and the E register contents to the next direct data memory location. The DA value must be an even number. If it is an odd number, the LSB of the DA value is recognized as logic zero (an even number), and is not replaced with the true value. Load contents of EA to the 8-bit RRb register (HL, WX, YZ). The E register is loaded into the H, W, and Y register and the A register into the L, X, and Z register. Load the A register to data memory location pointed to by the 8-bit HL register, and the E register contents to the next location, HL + 1. The contents of the L register must be an even number. If the number is odd, the LSB of the L register is recognized as logic zero (an even number), and is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to register HL; the instruction 'LD @HL,EA' loads the contents of A into address 36H and the contents of E into address 37H. LD EA,DA LD EA,RRb LD @HL,A LD DA,EA LD RRb,EA LD @HL,EA % LDB LDB Operation: dst,src.b dst.b,src Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load memory bit to a specified carry bit Load indirect memory bit to a specified carry bit Operation Summary Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Bytes 2 2 2 2 2 2 Cycles 2 2 2 2 2 2 Description: The Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. One of the operands must be the carry flag; the other may be any directly or indirectly addressable bit. The source is unaffected. Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b* C,memb.@L C,@H+DA.b 1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 b1 1 1 0 1 b1 Binary Code 1 1 0 1 b0 1 1 0 1 b0 1 1 a5 1 a3 0 0 a5 0 a3 1 1 a4 1 a2 1 1 a4 1 a2 0 0 a3 0 a1 0 0 a3 0 a1 0 0 a2 0 a0 0 0 a2 0 a0 C [H + DA.3-0].b C mema.b C memb.7-2 + [L.3-2] . [L.1-0] H + [DA.3-0].b (C) Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C Second Byte Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH mema.b 1 1 0 1 b1 b1 b0 b0 a3 a3 % LDB Examples: (Continued) 1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction clears the carry flag to logic zero. LDB C,P1.0 2. The P1 address is FF1H and the L register contains the value 1H (0001B). The address (memb.7-2) is 111100B and (L.3-2) is 00B. The resulting address is 11110000B or FF0H and P0 is addressed. The bit value (L.1-0) is specified as 01B (bit 1). LD LDB L,#0001B C,P1.@L ; P1.@L specifies P0.1 and C P0.1 3. The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for FLAG(3-0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value is 3. Therefore, @H+FLAG = 20H.3. FLAG LD LDB EQU 20H.3 H,#2H C,@H+FLAG ; C FLAG (20H.3) 4. The following instruction sequence sets the carry flag and the loads the "1" data value to the output pin P1.0, setting it to output mode: SCF LDB P1.0,C ; C "1" ; P1.0 "1" 5. The P1 address is FF1H and L = 01H (0001B). The address (memb.7-2) is 111100B and (L.32) is 00B. The resulting address, 11110000B specifies P0. The bit value (L.1-0) is specified as 01B (bit 1). Therefore, P1.@L = P0.1. SCF LD LDB ; C "1" L,# 0001B P1.@L,C ; P1.@L specifies P0.1 ; P0.1 "1" 6. In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit value is 3, @H+FLAG = 20H.3: FLAG RCF LD LDB EQU 20H.3 ; C "0" ; FLAG(20H.3) "0" H,#2H @H+FLAG,C , # 9 6 : % %'"' LDC Operation: dst,src Operand EA,@WX EA,@EA Operation Summary Load code byte from WX to EA Load code byte from EA to EA Bytes 1 1 Cycles 3 3 Description: This instruction is used to load a byte from program memory into an extended accumulator. The address of the byte fetched is the six highest bit values in the program counter and the contents of an 8-bit working register (either WX or EA). The contents of the source are unaffected. Operand EA,@WX EA,@EA 1 1 1 1 0 0 Binary Code 0 0 1 1 1 0 0 0 0 0 Operation Notation EA [PC14-8 + (WX)] EA [PC14-8 + (EA)] Examples: 1. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: LD CALL JPS ORG DB DB DB DB LDC RET EA,#00H DISPLAY MAIN 0500H 66H 77H 88H 99H EA,@EA ; EA address 0500H = 66H DISPLAY If the instruction 'LD EA,#01H' is executed in place of 'LD EA,#00H', The content of 0501H (77H) is loaded to the EA register. If 'LD EA,#02H' is executed, the content of address 0502H (88H) is loaded to EA. % %'"' LDC Examples: (Continued) 2. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: ORG DB DB DB DB LD LDC RET 0500H 66H 77H 88H 99H WX,#00H EA,@WX ; EA address 0500H = 66H DISPLAY If the instruction 'LD WX,#01H' is executed in place of 'LD WX,#00H', then EA address 0501H = 77H. If the instruction 'LD WX,#02H' is executed in place of 'LD WX,#00H', then EA address 0502H = 88H. 3. Normally, the LDC EA, @EA and the LDC EA, @WX instructions reference the table data on the page on which the instruction is located. If, however, the instruction is located at address xxFFH, it will reference table data on the next page. In this example, the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A: 01FDH 01FFH ORG LD LDC 01FDH WX,#00H EA,@WX ; E upper 4 bits of 0200H address ; A lower 4 bits of 0200H address 4. Here is another example of page referencing with the LDC instruction: ORG DB SMB LD LD LDC LD 0100H 67H 0 HL,#30H ; Even number WX,#00H EA,@WX ; E upper 4 bits of 0100H address ; A lower 4 bits of 0100H address @HL,EA ; RAM (30H) 7, RAM (31H) 6 %'2%!"'+!'2' LDD Operation: dst Operand A,@HL Operation Summary Load indirect data memory contents to A; decrement register L contents and skip on borrow Bytes 1 Cycles 2+S Description: The contents of a data memory location are loaded into the accumulator, and the contents of the register L are decreased by one. If a "borrow" occurs (e.g., if the resulting value in register L is 0FH), the next instruction is skipped. The contents of data memory and the carry flag value are not affected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH Example: In this example, assume that register pair HL contains 20H and internal RAM location 20H contains the value 0FH: LD LDD JPS JPS HL,#20H A,@HL XXX YYY ; A (HL) and L L-1 ; Skip ; H 2H and L 0FH The instruction 'JPS XXX' is skipped since a "borrow" occurred after the 'LDD A,@HL' and instruction 'JPS YYY' is executed. %'2%!"+!'2' LDI Operation: dst,src Operand A,@HL Operation Summary Load indirect data memory to A; increment register L contents and skip on overflow Bytes 1 Cycles 2+S Description: The contents of a data memory location are loaded into the accumulator, and the contents of the register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L is 0H), the next instruction is skipped. The contents of data memory and the carry flag value are unaffected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H Example: Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value 0FH: LD LDI JPS JPS HL,#2FH A,@HL XXX YYY ; A (HL) and L L+1 ; Skip ; H 2H and L 0H The instruction 'JPS XXX' is skipped since an overflow occurred after the 'LDI A,@HL' and the instruction 'JPS YYY' is executed. 5-2$ JP Operation: dst Operand ADR15 Operation Summary Jump to direct address (15 bits) Bytes 3 Cycles 3 Description: JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. The destination can be anywhere in the 32-Kbyte program memory address space. The LJP instruction can be used in the all range (0000H-7FFFH) while the JP instruction can be used in the only range (0000H-3FFFH). Operand ADR15 1 0 a7 1 a6 0 a5 Binary Code 1 a4 1 a3 0 a2 0 a9 a1 0 a8 a0 a14 a13 a12 a11 a10 Operation Notation PC14-0 ADR15 Example: The label 'SYSCON' is assigned to the instruction at program location 5FFFH. The instruction LJP SYSCON at location 0123H will load the program counter with the value 5FFFH. %$'!% NOP Operation: Operand - No operation Operation Summary Bytes 1 Cycles 1 Description: No operation is performed by a NOP instruction. It is typically used for timing delays. One NOP causes a 1-cycle delay: with a 1 s cycle time, five NOPs would therefore cause a 5 s delay. Program execution continues with the instruction immediately following the NOP. Only the PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction. Operand - 1 0 1 Binary Code 0 0 0 0 0 Operation Notation No operation Example: Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power-down mode is initiated: STOP NOP NOP NOP %*+) OR Operation: dst,src Operand A, #im A, @HL EA,RR RRb,EA Operation Summary Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Bytes 2 1 2 2 Cycles 2 1 2 2 Description: The source operand is logically ORed with the destination operand. The result is stored in the destination. The contents of the source are unaffected. Operand A, #im A, @HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 0 1 1 0 1 0 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 0 0 0 0 0 RRb RRb OR EA A A OR (HL) EA EA OR RR Operation Notation A A OR im Example: If the accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction OR EA,@HL leaves the value 0D7H (11010111B) in the accumulator . %$(!%2+# POP Operation: dst Operand RR SB Operation Summary Pop to register pair from stack Pop SMB and SRB values from stack Bytes 1 2 Cycles 1 2 Description: The contents of the RAM location addressed by the stack pointer is read, and the SP is incremented by two. The value read is then transferred to the variable indicated by the destination operand. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 0 1 0 Operation Notation RR& (SP), RR; (SP+1) SP SP+2 (SRB) (SP), SMB (SP+1), SP SP+2 Example: The SP value is equal to 0EDH, and RAM locations 0EFH through 0EDH contain the values 2H, 3H, and 4H, respectively. The instruction POP HL leaves the stack pointer set to 0EFH and the data pointer pair HL set to 34H. -, PUSH Operation: src %+# Operand RR SB Operation Summary Push register pair onto stack Push SMB and SRB values onto stack Bytes 1 2 Cycles 1 2 Description: The SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer, thereby adding a new element to the top of the stack. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 1 1 1 Operation Notation (SP-1) RR;, (SP-2) RR& SP SP-2 (SP-1) SMB, (SP-2) SRB; (SP) SP-2 Example: As an interrupt service routine begins, the stack pointer contains the value 0FAH and the data pointer register pair HL contains the value 20H. The instruction PUSH HL leaves the stack pointer set to 0F8H and stores the values 2H and 0H in RAM locations 0F9H and 0F8H, respectively. ',' !!" )* RCF Operation: Operand - Operation Summary Reset carry flag to logic zero Bytes 1 Cycles 1 Description: The carry flag is cleared to logic zero, regardless of its previous value. Operand - 1 1 1 Binary Code 0 0 1 1 0 C0 Operation Notation Example: Assuming the carry flag is set to logic one, the instruction RCF resets (clears) the carry flag to logic zero. '('!'+',!-+% REF Operation: dst Operand memc Reference code Operation Summary Bytes 1 Cycles 3 , 34 5<%&& Description: The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the REF instruction reference area in program memory. REF reduces the number of program memory accesses for a program. Operand memc t7 t6 t5 Binary Code t4 t3 t2 t1 t0 Operation Notation PC13-0 memc.7-4, memc.3-0 < 1 TJP and TCALL are 2-byte pseudo-instructions that are used only to specify the reference area: 1. When the reference area is specified by the TJP instruction, memc.7-6 = 00 PC13-0 memc.5-0 + (memc + 1).7-0 2. When the reference area is specified by the TCALL instruction, memc.7-6 = 01 [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8 SP SP-6 PC13-0 memc.5-0 + (memc + 1).7-0 When the reference area is specified by any other instruction, the 'memc' and 'memc + 1' instructions are executed. Instructions referenced by REF occupy 2 bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020H to 007FH in ROM. In addition, the destination address of the TJP and TCALL instructions must be located with the 3FFFH address. TJP and TCALL are reference instructions for JP/JPS and CALL/CALLS. If the instruction following a REF is subject to the 'redundancy effect', the redundant instruction is skipped. If, however, the REF follows a redundant instruction, it is executed. On the other hand, the binary code of a REF instruction is 1 byte. The upper 4 bits become the higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction becomes the lower address, producing a total of 8 bits or 1 byte (see Example 3 below). , 2* = -./$ 34 '('!'+',!-+% REF Examples: (Continued) 1. Instructions can be executed efficiently using REF, as shown in the following example: AAA BBB CCC DDD ORG LD LD TCALL TJP 0020H HL,#00H EA,#FFH SUB1 SUB2 ORG REF REF REF REF 0080H AAA BBB CCC DDD ; ; ; ; LD LD CALL JP HL,#00H EA,#FFH SUB1 SUB2 2. The following example shows how the REF instruction is executed in relation to LD instructions that have a 'redundancy effect': AAA ORG LD 0020H EA,#40H ORG LD REF 0100H EA,#30H AAA ; Not skipped REF LD SRB AAA EA,#50H ; Skipped 2 '('!'+',!-+% REF Examples: (Concluded) 3. In this example the binary code of 'REF A1' at locations 20H-21H is 20H, for 'REF A2' at locations 22H-23H, it is 21H, and for 'REF A3' at 24H-25H, the binary code is 22H : Opcode Symbol Instruction ORG 0020H HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2 83 83 83 83 83 83 83 83 83 41 01 00 03 05 10 26 08 0F F0 67 0B 0D A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 LD LD LD LD LD LD LD LD LD TCALL TJP ORG 0100H A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ; ; ; ; ; ; ; ; ; ; ; LD LD LD LD LD LD LD LD LD CALL JP HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2 20 21 22 23 24 25 26 27 30 31 32 REF REF REF REF REF REF REF REF REF REF REF '-!(!%2-4!%-' RET Operation: Operand - Operation Summary Return from subroutine Bytes 1 Cycles 3 Description: RET pops the PC values successively from the stack, incrementing the stack pointer by six. Program execution continues from the resulting address, generally the instruction immediately following a CALL, LCALL or CALLS. Operand - 1 1 0 Binary Code 0 0 1 0 1 Operation Notation PC14-8 (SP+1) (SP) PC7-0 (SP+3) (SP+2) EMB,ERB (SP+5) (SP+4) SP SP+6 Example: The stack pointer contains the value 0FAH. RAM locations 0FAH, 0FBH, 0FCH, and 0FDH contain 1H, 0H, 5H, and 2H, respectively. The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H. During a return from subroutine, PC values are popped from stack locations as follows: SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 (0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (000H) 0 0 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0 %'++-2-)%!* RRC Operation: A Operand A !%-* !!" Operation Summary Rotate right through carry bit Bytes 1 Cycles 1 Description: The four bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position. + % . Operand A 1 0 0 Binary Code 0 1 0 0 0 Operation Notation C A.0, A3 C A.n-1 A.n (n = 1, 2, 3) Example: The accumulator contains the value 5H (0101B) and the carry flag is cleared to logic zero. The instruction RRC A leaves the accumulator with the value 2H (0010B) and the carry flag set to logic one. -4!+ SBC Operation: dst,src Operand A,@HL EA,RR RRb,EA !!" Operation Summary Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2 Description: SBC subtracts the source and carry flag value from the destination operand, leaving the result in the destination. SBC sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. The contents of the source are unaffected. If the carry flag was set before the SBC instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. In this case, the carry bit is subtracted from the destination along with the source operand. Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 0 0 0 0 0 C,RRb RRb - EA - C Operation Notation C,A A - (HL) - C C, EA EA -RR - C Examples: 1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF SBC JPS EA,HL XXX ; C "1" ; EA 0C3H - 0AAH - 1H, C "0" ; Jump to XXX; no skip after SBC 2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF SBC JPS EA,HL XXX ; C "0" ; EA 0C3H - 0AAH - 0H = 19H, C "0" ; Jump to XXX; no skip after SBC -4!+ SBC Examples: (Continued) !!" 3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on 'no borrow' to the instruction immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'SBC A,@HL' instruction does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. a. 8 - 6 decimal addition (the contents of the address specified by the HL register is 6H): RCF LD SBC ADS JPS A,#8H A,@HL A,#0AH XXX ; ; ; ; C "0" A 8H A 8H - 6H - C(0) = 2H, C "0" Skip this instruction because no borrow after SBC result b. 3 - 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD SBC ADS JPS A,#3H A,@HL A,#0AH XXX ; ; ; ; ; ; C "0" A 3H A 3H - 4H - C(0) = 0FH, C "1" No skip. A 0FH + 0AH = 9H (The skip function of 'ADS A,#im' is inhibited after a 'SBC A,@HL' instruction even if an overflow occurs.) -4!+ SBS Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Bytes 1 2 2 Cycles 1+S 2+S 2+S Description: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. A skip is executed if a borrow occurs. The value of the carry flag is not affected. Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 1 0 0 0 0 RRb RRb - EA; skip on borrow Operation Notation A A - (HL); skip on borrow EA EA - RR; skip on borrow Examples: 1. The accumulator contains the value 0C3H, register pair HL contains the value 0C7H, and the carry flag is cleared to logic zero: RCF SBS JPS JPS EA,HL XXX YYY ; ; ; ; ; ; C "0" EA 0C3H - 0C7H SBS instruction skips on borrow, but carry flag value is not affected Skip because a borrow occurred Jump to YYY is executed 2. The accumulator contains the value 0AFH, register pair HL contains the value 0AAH, and the carry flag is set to logic one: SCF SBS JPS EA,HL XXX ; ; ; ; ; C "1" EA 0AFH - 0AAH Jump to XXX JPS was not skipped since no "borrow" occurred after SBS ' !!" )* SCF Operation: Operand - Operation Summary Set carry flag to logic one Bytes 1 Cycles 1 Description: The SCF instruction sets the carry flag to logic one, regardless of its previous value. Operand - 1 1 1 Binary Code 0 0 1 1 1 C1 Operation Notation Example: If the carry flag is cleared to logic zero, the instruction SCF sets the carry flag to logic one. ')'+'2%!"# SMB Operation: n Operand n Operation Summary Select memory bank Bytes 2 Cycles 2 Description: The SMB instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. The constants 0, n, and 15 are usually used as the SMB operand to select the corresponding memory bank. All references to data memory addresses fall within the following address ranges: Please note that since data memory spaces differ for various devices in the SAM4 product family, the 'n' value of the SMB instruction will also vary. Addresses 000H-01FH 020H-0FFH n00H-nFFH F80H-FFFH Register Areas Working registers Stack and general-purpose registers General-purpose registers I/O-mapped hardware registers n (n = 1-14) 15 n (n = 1-14) 15 Bank 0 SMB 0 The enable memory bank (EMB) flag must always be set to "1" in order for the SMB instruction to execute successfully for memory banks 0-15. Format n 1 0 1 1 0 0 Binary Code 1 0 1 d3 1 d2 0 d1 1 d0 Operation Notation SMB n (n = 0-15) Example: If the EMB flag is set, the instruction SMB 0 selects the data memory address range for bank 0 (000H-0FFH) as the working memory bank. , ) * ')'+'*,'!# SRB Operation: n Operand n Operation Summary Select register bank Bytes 2 Cycles 2 Description: The SRB instruction selects one of four register banks in the working register memory area. The constant value used with SRB is 0, 1, 2, or 3. The following table shows the effect of SRB settings: ERB Setting 3 0 1 0 0 SRB Settings 2 0 0 1 x 0 0 1 1 , >9>1 Selected Register Bank 0 x 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3 The enable register bank flag (ERB) must always be set for the SRB instruction to execute successfully for register banks 0, 1, 2, and 3. In addition, if the ERB value is logic zero, register bank 0 is always selected, regardless of the SRB value. Operand n 1 0 1 1 0 0 Binary Code 1 1 1 0 1 0 0 d1 1 d0 Operation Notation SRB n (n = 0, 1, 2, 3) Example: If the ERB flag is set, the instruction SRB 3 selects register bank 3 (018H-01FH) as the working memory register bank. '-!(!%2-4!%-'#$ SRET Operation: Operand - Operation Summary Return from subroutine and skip Bytes 1 Cycles 3+S Description: SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL, LCALL or CALLS instruction. SRET skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. Then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. Operand - 1 1 1 Binary Code 0 0 1 0 1 Operation Notation PC14-8 (SP+1) (SP) PC7-0 (SP+3) (SP+2) EMB,ERB (SP+5) (SP+4) SP SP+6 Example: If the stack pointer contains the value 0FAH and RAM locations 0FAH, 0FBH, 0FCH, and 0FDH contain the values 1H, 0H, 5H, and 2H, respectively, the instruction SRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0125H, then skips unconditionally. During a return from subroutine, data is popped from the stack to the PC as follows: SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 (0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (000H) 0 0 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0 %$$'!% STOP Operation: Operand - Operation Summary Engage CPU stop mode Bytes 2 Cycles 2 Description: The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON) to logic one. When STOP executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. Operand - 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 1 Operation Notation PCON.3 1 Example: Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception of some peripheral hardware). The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed. %66'+%!!',, VENTn Operation: dst Operand EMB (0,1) ERB (0,1) ADR Operation Summary Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location. Bytes 2 Cycles 2 Description: The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable register bank flag (ERB) into the respective vector addresses. It then points the interrupt service routine to the corresponding branching locations. The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. After the return from interrupt (IRET) you do not need to set the EMB and ERB values again. Instead, use BITR and BITS to clear these values in your program routine. The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction. These starting addresses must be located in ROM ranges 0000H-3FFFH. Generally, the VENTn instructions are coded starting at location 0000H. The format for VENT instructions is as follows: VENTn d1,d2,ADDR EMB d1 ("0" or "1") ERB d2 ("0" or "1") PC ADDR (address to branch n = device-specific module address code (n = 0-n) Operand EMB (0,1) ERB (0,1) ADR E M B E R B Binary Code a13 a12 a11 a10 a9 a8 Operation Notation ROM (2 x n) 7-6 EMB, ERB ROM (2 x n) 5-4 PC13-12 ROM (2 x n) 3-0 PC11-8 ROM (2 x n + 1) 7-0 PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0 %66'+%!!',, VENTn Example: (Continued) The instruction sequence ORG VENT0 VENT1 VENT2 VENT3 VENT4 VENT6 VENT7 0000H 1,0,RESET 0,1,INTA 0,1,INTB 0,1,INTC 0,1,INTD 0,1,INTE 0,1,INTF causes the program sequence to branch to the RESET routine labeled 'RESET', setting EMB to "1" and ERB to "0" when is activated. When a basic timer interrupt is generated, VENT1 causes the program to branch to the basic timer's interrupt service routine, INTA, and to set the EMB value to "0" and the ERB value to "1". VENT2 then branches to INTB, VENT3 to INTC, and so on, setting the appropriate EMB and ERB values. , ?3@ 9 /+ XCH Operation: *'%! 44)'%!"' dst,src Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL Operation Summary Exchange A and data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Bytes 2 1 1 2 2 2 Cycles 2 1 1 2 2 2 Description: The instruction XCH loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL 0 a7 0 0 1 a7 1 1 1 0 1 a6 1 1 1 a6 1 1 1 0 1 a5 1 1 0 a5 0 1 0 0 Binary Code 1 a4 0 1 0 a4 1 0 1 0 1 a3 1 1 1 a3 1 0 1 0 0 a2 r2 i2 1 a2 1 r2 1 0 0 a1 r1 i1 1 a1 0 r1 0 0 1 a0 r0 i0 1 a0 0 0 0 1 A (HL), E (HL + 1) EA RRb A Ra A (RRa) A DA,E DA + 1 Operation Notation A DA Example: Double register HL contains the address 20H. The accumulator contains the value 3FH (00111111B) and internal RAM location 20H the value 75H (01110101B). The instruction XCH EA,@HL leaves RAM location 20H with the value 3FH (00111111B) and the extended accumulator with the value 75H (01110101B). /+ XCHD Operation: *''+!'2' dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; decrement contents of register L and skip on borrow Bytes 1 Cycles 2+S Description: The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L. If the content of register L is 0FH, the next instruction is skipped. The value of the carry flag is unaffected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH Example: Register pair HL contains the address 20H and internal RAM location 20H contains the value 0FH: LD LD XCHD JPS JPS XCHD YYY HL,#20H A,#0H A,@HL XXX YYY A,@HL ; ; ; ; A 0FH and L L - 1, (HL) "0" Skipped since a borrow occurred H 2H, L 0FH (2FH) 0FH, A (2FH), L L - 1 = 0EH The 'JPS YYY' instruction is executed since a skip occurs after the XCHD instruction. /+ XCHI Operation: *'+!'2' dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; increment contents of register L and skip on overflow Bytes 1 Cycles 2+S Description: The instruction XCHI exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then increments the contents of register L. If the content of register L is 0H, a skip is executed. The value of the carry flag is unaffected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H Example: Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH: LD LD XCHI JPS JPS XCHI YYY HL,#2FH A,#0H A,@HL XXX YYY A,@HL ; ; ; ; A 0FH and L L + 1 = 0, (HL) "0" Skipped since an overflow occurred H 2H, L 0H (20H) 0FH, A (20H), L L + 1 = 1H The 'JPS YYY' instruction is executed since a skip occurs after the XCHI instruction. %*+)/+)-,&' XOR Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Bytes 2 1 2 2 Cycles 2 1 2 2 Description: XOR performs a bitwise logical XOR operation between the source and destination variables and stores the result in the destination. The source contents are unaffected. Operand A,#im A,@HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 0 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb XOR EA A A XOR (HL) EA EA XOR (RR) Operation Notation A A XOR im Example: If the extended accumulator contains 0C3H (11000011B) and register pair HL contains 55H (01010101B), the instruction XOR EA,HL leaves the value 96H (10010110B) in the extended accumulator. |
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